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- The size of pmos pass transistor in LDO regulator
pmos pass transistor Hi, all I am designing a LDO regulator, the minimal power supply voltage is 4 75V, and the output voltage is 4 5V, the maximum output current is 20mA In order to assure the pmos pass transistor operating in saturation, I have to set a large W L, but i can not provide this
- [SOLVED] - Slewing and Overshoot in LDO during Powerup
Hi, I have a three stage LDO with an external capacitor and PMOS pass device During Power up, the external capacitor has to be charged up and hence the Pass device is fully ON, i e , the LDO is slewing My problem is that in some cases corners, the Output voltage overshoots the reference
- The difference between ground current and quiescent current
hI GUYS IS THERE ANY DIFFERENCE BETWEEN GROUND CURRENT AND QUISCENT CURRENT IN LDO DESIGN? IS THERE MEANS CAN YOU GIVE INFORMATION ON THIS?
- Interview Questions on low drop out regulator
power electronics interview questions hi to all can anybody has a link from which i will get the interview questions may be asked before or possible to ask for one electronics engineer? basically questions required on the subject are: -Microcontroller -Microprocessor -VLSI -DSP -Power
- How to improve LDOs transient response? | Forum for Electronics
ldo frequency and transient response Some commercial chips like TI's add comparators to control overshoot and undershoot When undershoot is detected, sourcing current will be increased and when overshoot is detected, a sinking current will pull low the output
- How to properly do AC open loop LDO simulation?
ldo simulation setup in hspice there is a resistance that when dc the value is zero, but when ac, it is open Can we just use the thing?
- operating region of pass element in LDO - Forum for Electronics
I am really confused What is the operating region of pass element in LDO (Low Dropout Linear Regulator)? I see a lot of documents saying that it operates in linear mode However, in this page, at slide 37, the author considered the power MOS operating in saturation for that calculation Could
- LDO design issue - no load condition | Forum for Electronics
Hi I am working on a LDO design that requires a rather large PMOS pass transistor due to the specified max current I have issues with pulling the pass transistor gate high enough at no load conditions to avoid the output voltage creeping upwards due to leakage in the pass transistor In
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