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- The size of pmos pass transistor in LDO regulator
pmos pass transistor Hi, all I am designing a LDO regulator, the minimal power supply voltage is 4 75V, and the output voltage is 4 5V, the maximum output current is 20mA In order to assure the pmos pass transistor operating in saturation, I have to set a large W L, but i can not provide this
- LDO design issue - no load condition | Forum for Electronics
Hi I am working on a LDO design that requires a rather large PMOS pass transistor due to the specified max current I have issues with pulling the pass transistor gate high enough at no load conditions to avoid the output voltage creeping upwards due to leakage in the pass transistor In
- Comparison of LDO and level shifter | Forum for Electronics
Re: LDO vs Level shifter The main benefit of an LDO over a buck converter is lower noise However, the efficiency is worse especially for large voltage drops 12 V to 3 3 V implies an efficiency of 28% for the LDO, vs 80-90% for the buck
- A Low Power NMOS LDO in the Philips CO50PMU Process - Forum for Electronics
In this report a new architecture of an NMOS Low Drop Out (LDO) Regulator is proposed It features a new frequency compensation technique to enable better regulation The LDO Regulator handles large load currents with good stability (25° phase margin for low load currents from no load till 2mA and then towards
- behavioral modelling for LDO | Forum for . . . - Forum for Electronics
verilog-a ldo Thanx sunking and sixth, now to start with my design, i have nmos and pmos devices categorized as Logic , MM and RF can someone explain what exactly Logic, MM and RF devices means are they modelled differently?? cant i use an RF or logic device to design an LDO any document regarding this would be very helpful thanx in advance
- Pass transistor in LDO - Forum for Electronics
Pass transistor in LDO Thread starter kishore680; Start date Jun 17, 2013; Jun 17, 2013 #1 K
- How to properly do AC open loop LDO simulation?
ac analysis of ldo I also confused it, sometimes, I use the AC source with ac=1V to break the loop sometime, I use the resistor with AC=1G , and a cap=1F and sometime, I use the ind=1G and a cap =1F the only diff thing I thought is the phase of it different But offten, the gain plot is also diff
- [SOLVED] - LDO Output resistance. - Forum for Electronics
rds is a static (DC) parameter, the output impedance is a dynamic (small signal) parameter Due to the LDO regulation mechanism with nearly full feedback, i e gain≈1, the (low frequency) output impedance -- in a 1 st (coarse) approximation -- is rds A ol-- A ol being the open loop gain of the LDO So your tf analysis result seems quite correct
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