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Gearing Up Serdes for High-Speed Operation - EE Times To solve this problem, designers can turn to several options that reduce the clock and parallel data frequency to within range of the ATE equipment These options include increasing the parallel data width, using an on-die clock doubling circuit, or using dual data rate (DDR) clocks
20 GHz SerDes TX RX Loopback Testing - Amphenol Ardent Concepts The chip has a loopback that does not use the last stage of the TX driver so the customer was able to test using different transmitter signal output levels to run transmitter into receiver with this loopback solution
SERDES external loopback test using production parametric-test hardware . . . This paper describes a dedicated production load-board that is designed to achieve tester access on the SERDES pins using a resistor network Using this load-board, external loopback could be operated successfully up to 20Gbps without sacrificing parametric test capability
18-bit SerDes Design Guide (DS92LV18, SCAN921821) - Texas Instruments They are similar to the original 10- and 16- bit Bus LVDS SerDes products, but provide a wider, 18-bit data bus payload to support not only byte-oriented data but also carry other information such as parity, frame, control, status, sync, low frequency bus or clock signals, etc
Performing Internal and External Loopback Tests on SerDes of T1042 . . . What are the steps to configure and execute an internal loopback test on the SerDes module of the T1042 processor? Which specific SerDes registers or settings need to be adjusted for this test? How can I verify the test results to confirm the SerDes is operating correctly in internal loopback mode?
C6457 SERDES Loopback test - Processors forum - TI E2E support forums When advacnein on to a loopback test for SWERDES, it fails What are common pitfalls that we may be missing in getting this test to work properly? We are referencing the SPRUGK9 PDF, TMS320C6457 DSP Ethernet Media Access Controller (EMAC) Management Data Input Output (MDIO) User's Guide
TCI6638K2K: SERDES Loopback Mode - TI E2E support forums I have questions about LB_FEP (Far-End Loopback) of "19 2 Loopbacks" in SerDes User's Guide (SPRUHO3A) There is showed "Figure 19-1 Internal Loopback Modes" in "19 2 Loopbacks" Customers would like to set the parameters described - Table 14-3 TX Driver Register Signals for PHY-A - Table 14-4 TX Driver Register Signals for PHY-B