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LS1021A PCIe iATU configuration - NXP Community So effectively the iATU is translating the 40-bit BAR space physical address to 32-bit PCIe address space which is fine My question is why the default configuration only programs the outbound and not the inbound as well? Is it not expected that the PCIe device will write to this BAR space area at address 0x40 0000 0000?
AM5726: Inbound and outbound connection in PCIe The iATU registers support up to 16 inbound and outbound translation regions The iATU registers are not initially mapped to the standard PCIe configure space, so they can be either setup by the EP software by itself, or RC need to specifically copy the iATU register content to the EP
Reserving physical memory, then directing pcie packets to there by . . . To achieve this, in the NX, we need to reserve a specific memory address and direct PCIe packets to that memory with inbound address translation unit of the pcie controller, then redirect pcie memory to that reserved space for this communication to be inbound (I know this is achievable, we previously did the same with some other chip )
LKML: Serge Semin: [PATCH v2 11 17] PCI: dwc: Simplify in outbound iATU . . . From maintainability and scalability points of view it has been wrong to use different iATU inbound and outbound regions accessors for the viewport and unrolled versions of the iATU CSRs mapping Seeing the particular iATU region-wise registers layout is almost fully compatible for different IP-core versions, there were no much points in splitting the code up that way since it was possible to
LS102xA: PCIe ATU inbound configuration - NXP Community In our application, the FPGA is the only endpoint connected to the LS1021A SoC over PCIe bus From the FPGA we need to access CCSR and OCRAM areas as inbound memory read The CCSR is at physical address 0x100 0000 and OCRAM at physical address 0x1000 0000 We are going to use Flat PCI bus addres
How to correctly program inbound address translation unit? Hey everyone, I have an FPGA connected from PCIe to a Xavier NX NX is the host, the other device is the endpoint The scenario is, FPGA initiates a transaction to NX, and I want what is written via PCIe in my memory My question is: How to effectively correctly program iATU, and is this enough for me to achieve my goal? I guess I need to reserve a memory block from device tree, since I want
PCIe EP to EP inbound and outbound configurations Again as per the Inbound translation (BAR match mode) in Endpoint-2, data received from 0x40_4100_0000 should go to 0xA000_0000 which is iATU Target address offset inbound (Upper, Lower) But I don't see it working as expected Please firstly let me know, Is my understanding correct ? Thanks
AM6548: PCIe endpoint configuration - TI E2E support forums The TRM tells us that we ought to be able to have 32 iATU regions in each direction (instead of 16) if we use only 32-bit addresses (see 12 2 2 4 7 PCIe Subsystem Address Translation) - how can we configure these 32 regions?