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What does PHY refer to? - Electrical Engineering Stack Exchange a PHY is a type of Ethernet physical layer (eg 100BASE-TX, 10BASE-T) a PHY is an Ethernet transceiver IC (eg an IC that converts 100BASE-TX to MII RMII) a PHY is a physical layer device (more than just the transceiver IC) Is PHY ambiguous and can refer to all of these or did I understand something wrong?
Ethernet switch IC ports in MAC and PHY mode 1 for port 2 and 6, the phy is external Unfortunately though not all phy information is present on an RGMII GMII and this is sent over MDIO MDC The switch needs to know you have a phy connected, and hence that mode It's possible to connect RGMII GMII to another mac also and skip the phy 2 there is no internal phy if it comes out RGMII GMII, and if you are going from mac to mac there will
fpga - Problems in understanding PCIe blocks in Xilinx Vivado for . . . These two PHY are actually different, that IP vendor's PHY is below PIPE interface, only contains PCS and PMA, while the PHY in TLP DL PHY also contains PHY-MAC Knowing this difference in different context makes things a bit clear I guess
Connecting a PHY to another PHY on a same board Generally, if I'm connecting a PHY to RJ45 connector, I would add center tap capacitors and Bob-Smith termination like below But if I am connecting a PHY to another PHY, do I still need the Bob-Smith termination? Or can I just have center tap capacitors on both sides like below? Both PHYs share same GND but are powered by different rails
PHY address for SPI interface - Electrical Engineering Stack Exchange The "PHY address" you refer to is an bus address MDIO is a management interface between a MAC and one or more PHYs In the case of the W5500, the MAC and PHY are integrated in the chip Refer to the (green lines added by me): So there's no need for an external management interface, or for PHYAD pins
The SERDES transceiver design inside the Ethernet MAC controller The 1st and 2nd figures are normal application which transmits the data through copper media with coded information (through PCS PMD PMA inside the PHY chip) The interface between the MAC and PHY is SGMII or XAUI for 1G and 10G base-T Ethernet However, the 3rd figure confuses me
In USB, what is the difference between a PHY and a transceiver? A Phy is similar to a transceiver in that there is usually different signal standards on "both sides of the chip" With Ethernet it is MII GMII etc on one side and, well, Ethernet on the other
10BASE-T1S PHY circuit - Electrical Engineering Stack Exchange The intent is to deliver both power and 10 Mbps Ethernet data over a single conductor pair I understand 10BASE-T1S was designed to support a very simple PHY front-end implementation Are there any example circuits to do this? Is it based on the same magnetics as other twisted-pair Ethernet, or is capacitive coupling used?